1. Field of the Invention
The present invention generally relates to a method of removing a sacrificial light absorbing material and polymer residues that may remain on a substrate surface and inside openings during damascene structure preparation.
2. Description of the Related Art
Integrated circuits have evolved into complex devices that can include millions of components (e.g., transistors, capacitors and resistors) on a single chip. The evolution of chip designs continually requires faster circuitry and greater circuit density. The demands for greater circuit density necessitate a reduction in the dimensions of the integrated circuit components.
A dual damascene process is used to create the multi-level, high density metal interconnections needed for advanced, high performance integrated circuits (ICs). The initial transition to dual damascene employed copper metal with traditional silicon dioxide dielectric. More recently, the trend has moved toward the replacement of silicon dioxide dielectric with new low-k dielectric materials, such as carbon doped oxide (CDO).
The adoption of dual damascene copper metallization posed many challenges to the patterning process. Unacceptable variations in substrate reflectivity inhibited the well-controlled patterning of line and space on glass-like interlayer dielectric (ILD). Use of antireflective coating materials to suppress substrate reflectivity is a common practice in the industry. However, applying this technique to dual damascene patterning for sub-0.18 micron technology faces serious challenges in defect elimination and post-etch feature profile control.
A new material known as a sacrificial light absorbing material (SLAM) has recently been developed as an alternative to anti-reflective coating to address the problems mentioned above. SLAM has the light absorbing characteristics that suppress substrate reflectivity. It could be a dyed spin-on-glass (“SOG”) or a dyed spin-on-polymer (“SOP”) that is deposited by spin coating onto the substrate surface. Various methods of forming a dual damascene interconnect structure using SLAM are described in U.S. Pat. No. 6,448,185, titled “Method for Making a Semiconductor Device That Has a Dual Damascene Interconnect”, issued Sep. 10, 2002, and U.S. Pat. No. 6,365,529, titled “Method for Patterning Dual Damascene Interconnects Using a Sacrificial Light Absorbing Material”, issued Apr. 2, 2002.
The SLAM-based dual damascene processes mentioned above address defect elimination and post-etch feature profile control issues. However, the process requires a wet clean step to remove the remaining SLAM and etch residue. A wet clean step in a separate process system is time consuming and is limiting in its capability to control the post-etch feature profile. The term “etch” as recited herein is used broadly to include any material removal processes.
Therefore, a need exists in the art for a method of dry cleaning the sacrificial light absorbing material (SLAM) residue and post-etch polymer residue formed during the dual damascene patterning process.